Operating Multi-Node Full Fine-Tuning on NVIDIA B300
Reports checkpoint, NFS, page-cache, telemetry, and deadlock lessons from full fine-tuning a 32.76B model across two B300 nodes.
Caching, checkpointing, tiered memory, I/O, and distributed data management.
31 curated papers31 papers
Reports checkpoint, NFS, page-cache, telemetry, and deadlock lessons from full fine-tuning a 32.76B model across two B300 nodes.
Introduces Tensor-as-a-Service and a programmable distributed layer for weights, KV caches, checkpoints, and tensor movement.
Synthesizes safe, deployment-specific heuristics for cache eviction, tiered memory, and spot-VM scheduling using restricted generated code.
Measures aggregation, alignment, coalescing, buffered I/O, direct I/O, and io_uring for large-model checkpoint/restore workloads.
Transformer-based large language model (LLM) inference serving is now the backbone of many cloud services. LLM inference consists of a prefill phase and a decode phase.
In this article, we investigated the effects of cell variations, specifically the variations in gate length (${L}_{\text {g}}$), spacer length (${L}_{\text {s}}$), filler oxide thickness (${T}_{\text {f}}$), channel thickness (${T}_{\text {ch}}$), tunneling oxide thickness (${T}_{\text {tox}}$), charge trap nitride thickness (${T}_{\text {ctn}}$), and…
Fully Homomorphic Encryption (FHE) is a technique that allows arbitrary computations to be performed on encrypted data without the need for decryption, making it ideal for secure computation outsourcing. However, computation on FHE-encrypted data is significantly slower than that on plain data, primarily due to the explosive increases in data size and…
Sustainable and cost-effective long-term storage remains an unsolved problem. The most widely used storage technologies today are magnetic (hard disk drives and tape).
This article traces the evolution of SSD (solid-state drive) interfaces, examining the transition from the block storage paradigm inherited from hard disk drives to SSD-specific standards customized to flash memory. Early SSDs conformed to the block abstraction for compatibility with the existing software storage stack, but studies and deployments show…
Applies reinforcement learning to adapt cache size, queue depth, and readahead settings to changing I/O workloads.
Predicts write-only data so cloud block-storage caches can avoid low-value SSD writes and improve utilization.
Holographic Storage is an old idea that has always promised high density and fast random access, but has never been commercially competitive with Hard Disk Drives (HDDs) and Solid State Devices (SSDs). In Project HSD at Microsoft Research we asked the question: “Does holographic storage finally make sense for cloud storage?
The growing volume of graph data may exhaust the main memory. It is crucial to design a disk-based graph storage system to ingest updates and analyze graphs efficiently.
Major cloud providers have committed to lowering carbon emissions by 2030 across their datacenters, and research has contributed many ideas on how this may be achieved. However, a major contributor to datacenter emissions has not received enough attention: storage.
We propose an electron back-tunneling (EBT) method to enhance the retention characteristics of vertical NAND (V-NAND) flash memory. The storage of back-tunneled electrons in the spacer region between adjacent cells is facilitated by the synergistic effect of the fringing electric field between adjacent word-lines.
In this work, we have developed a large memory window (MW) ferroelectric field effect transistor (FeFET) memory for vertical NAND storage. We demonstrate that: 1) by inserting a top functional layer above the ferroelectric, gate side injection pumped by ferroelectric switching event can be enhanced, thus increasing the MW; 2) inspired by the charge trap…
We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al2O3 layer within the ferroelectric (FE) Hf$_{{0}.
We optimize the shape of the pulse to maximally increase threshold voltage (${V}_{\text {th}}\text {)}$during the incremental step pulse programming (ISPP) of vertical NAND (V-NAND) flash memory using neural networks (NNs). NN is trained using data on the increase in${V}_{\text {th}}$of commercial V-NAND flash memory in response to randomly shaped…
CXL-based disaggregated memory systems offer options to expand the memory beyond the limits of a single server via cache-coherent memory expansion cards or memory pools. Especially, In-Memory Database Management Systems (IMDBMSs) can benefit from alleviating two critical constraints: (1) limited memory capacity in a server and (2) long restart time…
This article overviews some of the key past developments in cloud data center power and energy management, where we are today, and what the future could be. This topic is gaining enormous renewed interest in the context of the conflicting needs of the AI revolution and the climate crisis.
A B-Tree is the most widely used range index for larger-than-memory data systems. It organizes data in pages (usually 4 KB) that efficiently align with disk IO operations, fully utilizing each IO operation to narrow down the search space.
This paper presents DDS, a novel disaggregated storage architecture enabled by emerging networking hardware, namely DPUs (Data Processing Units). DPUs can optimize the latency and CPU consumption of disaggregated storage servers.
The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe.
Learned indexes use machine learning techniques to improve index construction. However, they often face a fundamental trade-off between performance and memory consumption, especially in dynamic environments with frequent insert and delete operations.
The evolving data generation landscape requires faster and more efficient microprocessors, prompting innovative manufacturing methods for smaller and faster transistors. Transistor congestion and rising demand for parallel processing are pushing the thermal design power of microprocessors well beyond 280 W, a limit for air cooling, and are expected to…
Stream processing has been in widespread use, and one of the most common application scenarios is SQL query on streams. By 2021, the global deployment of IoT endpoints reached 12.
With the rapid development of blockchain and its applications, the amount of data stored on decentralized storage networks (DSNs) has grown exponentially. DSNs bring together affordable storage resources from around the world to provide robust, decentralized storage services for tens of thousands of decentralized applications (dApps).
CXL memory brings extra bandwidth and capacity via PCIe-based memory expansion beyond DDR-based DRAM. This paper introduces the CXL 2.
In this article, the endurance characteristic of 3-D NAND Flash memory is investigated. The bitline (BL) current and the word-line (WL) current are measured for erase/write (EW) cycling up to 50k.
Memory disaggregation is a promising architecture for modern datacenters that separates compute and memory resources into independent pools connected by ultra-fast networks, which can improve memory utilization, reduce cost, and enable elastic scaling of compute and memory resources. However, existing memory disaggregation solutions based on remote…
In order to improve the reliability of vertical NAND (V-NAND) flash memory cells, a scheme using adaptive incremental step pulse programming (A-ISPP) and incremental step pulse erasing (ISPE) is proposed. Incremental step pulse programming (ISPP) with adaptive step voltage is used to precisely adjust${V}_{\text {th}}$to a low target value while rapidly…